The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, a technology effective when applied to a semiconductor device having a nonvolatile memory and a manufacturing method thereof.
As an electrically programmable and erasable nonvolatile semiconductor memory device, EEPROM (Electrically Erasable and Programmable Read Only Memory) has been employed widely. Such a memory device (memory) typified by a flash memory which is used popularly now has, below a gate electrode of its MISFET, a conductive floating gate electrode encompassed by an oxide film or a charge trap insulating film. With the charge accumulation state in the floating gate or charge trap insulating film as memory, data, the device reads them as the threshold value of the transistor. This charge trap insulating film is an insulating film capable of accumulating charges therein and one example of it is a silicon nitride film. By injection of charges into a charge accumulation region or release therefrom, the threshold value of the MISFET is shifted to get the memory device to work. As this flash memory, a split gate cell using an MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film can be given as, one example. In such a memory, use of a silicon nitride film as a charge accumulation region is advantageous, because compared with a conductive floating gate film, it accumulates charges discretely so that it is excellent in the reliability of data retention. In addition, owing to excellent reliability of data retention, oxide films laid over and below the silicon nitride film can be thinned, making it possible to decrease the voltage for program and erase operations.
Japanese Patent Laid-Open No. 2002-231829 describes a technology of forming a select gate electrode over the surface of a channel region via a first gate insulating film, forming a sidewall-like control gate electrode over the side surface of the select gate electrode via a gate isolation insulating film while having a predetermined height difference between the control gate electrode and select gate electrode, and forming silicide layers over the surfaces of these gate electrodes, respectively, whereby these silicide layers formed over the respective gate electrodes can be insulated while spacing them closely, that is, without spacing them apart because there is a height difference between the control gate electrode and select gate electrode.